Standard

IEEE 1800.2-2020

Sep 2020 Current

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Language English

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Abstract

Revision Standard - Active. The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)

Products specifications

Standard from IEEE
Published: September 14 2020
Document type: IS
Pages
ISBN: 978-1-5044-6991-3

Publisher: IEEE
Distributor: IEEE
ICS: 35.060
National Committee: IEEE Computer Society / Design Automation

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Refers: IEEE 1800-2017
Refers: IEEE 1800-2017
Revises: IEEE 1800.2-2017

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Version history History (2)

IEEE 1800.2-2020

IEEE 1800.2-2017

Abstract

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