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Standard

IEEE 1800-2017

Revised

Note: Now under development: IEEE 1800-2023

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Abstract

Revision Standard - Superseded. The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.

Products specifications

  • Standard from IEEE
  • Published:
  • Document type: IS
  • Pages
  • Publisher: IEEE
  • Distributor: IEEE
  • ICS: 35.060
  • National Committee: IEEE Computer Society / Design Automation

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