Standard

IEEE 62530-2007

Dec 2007 Revised

Note: Latest version: IEEE 62530-2011

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Language English

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Abstract

New IEEE Standard - Superseded. This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI). This standard enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.

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Standard from IEEE/IEC
Published: December 9 2007
Document type: IS
Pages
ISBN: 9-7807-3815-7269

Publisher: IEEE/IEC
Distributor: IEEE/IEC
ICS: 25.040
ICS: 35.060
National Committee: IEEE Computer Society / Design Automation

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Version history History (2)

IEEE 62530-2011

IEEE 62530-2007

Abstract

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