Consolidated

IEC 62751-2:2014+AMD1:2019 CSV

Aug 2019 Current

Note: Latest version: IEC 62751-2:2014+AMD1:2019+AMD2:2023 CSV

Existing or new amendments and versions must be purchased separately.

Language English/French

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Abstract

IEC 62751-2:2014+A1:2019 gives the detailed method to be adopted for calculating the power losses in the valves for an HVDC system based on the "modular multi-level converter", where each valve in the converter consists of a number of self-contained, two-terminal controllable voltage sources connected in series. It is applicable both for the cases where each modular cell uses only a single turn-off semiconductor device in each switch position, and the case where each switch position consists of a number of turn-off semiconductor devices in series (topology also referred to as "cascaded two-level converter"). The main formulae are given for the two-level "half-bridge" configuration but guidance is also given as to how to extend the results to certain other types of MMC building block configuration. This consolidated version consists of the first edition (2014) and its amendment 1 (2019). Therefore, no need to order amendments in addition to this publication.

Products specifications

Consolidated from IEC
Published: August 23 2019
Edition: 1.1
Document type: IS
Pages
ISBN: 9782832273548

Publisher: IEC
Distributor: IEC
ICS: 29.200
ICS: 29.240.99
International TC: TC 22/SC 22F

Product Relations

Adopted by: NF EN 61298-4:1996

IEC 62751-2:2014+AMD1:2019 CSV

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IEC 62751-2:2014+AMD1:2019+AMD2:2023 CSV