Standard

IEC 61523-1:2023 ED3

Oct 2023 Current

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Language English

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Abstract

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. The standard specifications covered in this document are as follows: - Description language for timing and power modeling, called the “delay calculation language” (DCL) - Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions - Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF) - Informative usage examples - Informative notes. This is an IEC/IEEE dual logo standard.

Products specifications

Standard from IEEE
Published: October 11 2023
Edition: 3
Document type: IS
Pages
ISBN: 9782832275399

Publisher: IEEE
Distributor: IEEE
ICS: 25.040.01
ICS: 35.060
International TC: TC 91

Product Relations

Revises: IEC 61523-1:2012 ED2

IEC 61523-1:2023 ED3

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