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Standard

IEEE 1076.6-2004

Ritirato

Nota: Ultima versione: IEEE 1076.6-1999

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Le modifiche e le versioni esistenti o nuove devono essere acquistate separatamente.

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Astratto

Revision Standard - Inactive-Withdrawn. This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

Specifiche dei prodotti

  • Standard da IEEE
  • Pubblicato:
  • Ritirato:
  • Tipo di documento: IS
  • Pagine
  • Publisher IEEE
  • Distributor IEEE
  • ICS 35.060
  • National Committee IEEE Computer Society / Design Automation

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