Standard

IEC TR 62856:2013 ED1

Aug 2013 Current

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Language English/French

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Abstract

IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report: UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.

Products specifications

Standard from IEC
Published: August 7 2013
Edition: 1
Document type: TR
Pages
ISBN: 9782832210284

Publisher: IEC
Distributor: IEC
ICS: 25.040.01
ICS: 35.240.50
International TC: TC 91

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Version history Related Corrigenda and Amendments (0)

Abstract

Products specifications