Standard

IEC 62530:2011 ED2

May 2011 Revised

Note: Latest version: IEC 62530:2021 ED3

Existing or new amendments and versions must be purchased separately.

Language English

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Abstract

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

Products specifications

Standard from IEEE
Published: May 19 2011
Withdrawn: July 26 2021
Edition: 2
Document type: IS
Pages
ISBN: 9782889124503

Publisher: IEEE
Distributor: IEEE
ICS: 25.040.01
International TC: TC 91

Product Relations

Revised by: IEC 62530:2021 ED3
Revises: IEC 62530:2007 ED1
Adopted by: NF EN 60335-2-30:1993

IEC 62530:2011 ED2

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IEC 62530:2021 ED3